Neural Network Inference Accelerator
A 24-class ASL hand-sign classifier trained in PyTorch, then quantized and rebuilt as hardware — inference runs entirely on FPGA fabric at 100 MHz with no CPU and no external memory.
Hardware
Xilinx Artix-7 XC7A35T, Digilent Basys 3
RTL
Verilog, Vivado, DSP48E1 MAC Array
ML Pipeline
PyTorch, INT8 Post-Training Quantization
Verification
Golden Model, Self-Checking Testbenches, SymbiYosys
The Build
- Trained a 784→128→24 classifier in PyTorch, then built the accelerator to run that same network on-chip — weights live in block RAM, so nothing leaves the fabric at inference time
- Wrote an end-to-end Python quantization toolchain that computes per-layer scale factors, converts FP32 weights to INT8 using power-of-two shifts so rescaling reduces to a bit shift in hardware, and emits the memory initialization files the RTL loads
- Built a cycle-accurate Python golden model and a self-checking test harness that proved the implementation bit-exact against it, which caught quantization and overflow defects before anything reached the board
- Extending verification with SystemVerilog assertions discharged formally in SymbiYosys — proving accumulator overflow cannot occur for any legal input sequence, and that the datapath handshake is deadlock-free
Results
| Accuracy, FP32 baseline | 93% |
| Accuracy, INT8 on hardware | ~92% |
| Clock | 100 MHz |
| External memory | None |
| Softcore CPU | None |